A circuit design may include a plurality of latches, such as shift register latches (SRLs), which are catenated to form a level sensitive scan design (LSSD) scan chain. As a part of quality control, patterns of logic “0” and logic “1” may be shifted into scan chains to observe an output of a scan chain under test. Because the circuitry of the scan chain is wired in series, a fault encountered in the scan chain can obscure downstream determinations as to the functionality of scan chain components. As a result, an entire the logic circuit may be discarded, resulting in waste and inefficiency. Diagnosing failing locations can lead to fabrication process and design changes that improve later yield and reduce this waste.